diff --git a/arch/arm/boot/dts/imx6qdl-advantech.dtsi b/arch/arm/boot/dts/imx6qdl-advantech.dtsi
index 9fbcb15956..190866d891 100755
--- a/arch/arm/boot/dts/imx6qdl-advantech.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-advantech.dtsi
@@ -125,7 +125,7 @@
 		compatible = "pwm-backlight";
 		brightness-levels = <0 4 8 16 32 64 128 255>;
 		default-brightness-level = <7>;
-		status = "disabled";
+		status = "okay";
 	};
 
 	v4l2_capture_0: v4l2_cap_0 {
@@ -972,7 +972,7 @@
 
 &ldb {
 	status = "okay";
-	/* split-mode; */ /* dual-channel setting */
+	split-mode; /* dual-channel setting */
 
 	lvds-channel@0 {
 		fsl,data-mapping = "spwg";
@@ -984,15 +984,15 @@
 		display-timings {
 			native-mode = <&timing00>;
 			timing00: g070vw01v0 {
-				clock-frequency = <29500000>;
-				hactive = <800>;
-				vactive = <480>;
-				hback-porch = <96>;
-				hfront-porch = <24>;
-				vback-porch = <3>;
+				clock-frequency =<141860000>;
+				hactive = <1920>;
+				vactive = <1080>;
+				hback-porch = <35>;
+				hfront-porch = <35>;
+				vback-porch = <10>;
 				vfront-porch = <10>;
-				hsync-len = <72>;
-				vsync-len = <7>;
+				hsync-len = <35>;
+				vsync-len = <10>;
 			}; 
 
 			//SI Test panel
@@ -1049,22 +1049,23 @@
 	lvds-channel@1 {
 		fsl,data-mapping = "spwg";
 		fsl,data-width = <24>;
-		crtc = "ipu1-di1";
-		/* crtc = "ipu1-di0"; */ /* dual-channel setting */
+		/* crtc = "ipu1-di1"; */
+		crtc = "ipu1-di0"; /* dual-channel setting */
 		status = "okay";
 
 		display-timings {
 			native-mode = <&timing01>;
 			timing01: g070vw01v0 {
-				clock-frequency = <29500000>;
-				hactive = <800>;
-				vactive = <480>;
-				hback-porch = <96>;
-				hfront-porch = <24>;
-				vback-porch = <3>;
-				vfront-porch = <10>;
-				hsync-len = <72>;
-				vsync-len = <7>;
+				clock-frequency =<141860000>;
+                                hactive = <1920>;
+                                vactive = <1080>;
+                                hback-porch = <35>;
+                                hfront-porch = <35>;
+                                vback-porch = <10>;
+                                vfront-porch = <10>;
+                                hsync-len = <35>;
+                                vsync-len = <10>;
+
 			};
 
 			//SI Test panel
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index ad0897ac58..08bd178143 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -542,10 +542,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	}
 	clk[IMX6QDL_CLK_IPU1_SEL]         = imx_clk_mux("ipu1_sel",         base + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));
 	clk[IMX6QDL_CLK_IPU2_SEL]         = imx_clk_mux("ipu2_sel",         base + 0x3c, 14, 2, ipu_sels,          ARRAY_SIZE(ipu_sels));
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {
-		clk[IMX6QDL_CLK_LDB_DI0_SEL]      = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9,  3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
-		clk[IMX6QDL_CLK_LDB_DI1_SEL]      = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
-	} else {
+//	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) {
+//		clk[IMX6QDL_CLK_LDB_DI0_SEL]      = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9,  3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
+//		clk[IMX6QDL_CLK_LDB_DI1_SEL]      = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
+//	} else {
 		/*
 		 * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware
 		 * bug. Set the muxes to the requested values before registering the
@@ -555,7 +555,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 		init_ldb_clks(np);
 		clk[IMX6QDL_CLK_LDB_DI0_SEL]      = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9,  3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels));
 		clk[IMX6QDL_CLK_LDB_DI1_SEL]      = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels));
-	}
+//	}
 	clk[IMX6QDL_CLK_LDB_DI0_DIV_SEL]  = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);
 	clk[IMX6QDL_CLK_LDB_DI1_DIV_SEL]  = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);
 	clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
