Difference between revisions of "IoTGateway/BSP/Android/Gettingstarted/How to set LCD"

Revision as of 03:00, 3 February 2017

1. ROM 3420 (Current default display is LVDS)

a. If wanting to set LCD as default display, you can modify the device/fsl/rom_3420_a1/BoardConfig.mk as follows. 

BOARD_KERNEL_CMDLINE := console=ttymxc0,115200 init=/init <span style="color:#FF0000;">video=mxcfb0:dev=ldb,bpp=32</span> video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off vmalloc=256M androidboot.console=ttymxc0 consoleblank=0 androidboot.hardware=freescale cma=384M

For ROM7421 (Current default display is LVDS), please refer to device/fsl/rom_7421_a1/BoardConfig.mk

b. If you want to change the panel for your product, please modify the LDB parameters in /kernel_imx/arch/arm/boot/dts/imx6qdl-advantech.dtsi

Pleae refer to the Device-Tree bindings for LVDS Display Bridge (ldb) as follows

LVDS Display Bridge

=======

The LVDS Display Bridge device tree node contains up to two lvds-channel

nodes describing each of the two LVDS encoder channels of the bridge.

Required properties:

 - #address-cells : should be <1>

 - #size-cells : should be <0>

 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".

                Both LDB versions are similar, but i.MX6 has an additional

                multiplexer in the front to select any of the four IPU display

                interfaces as input for each LVDS channel.

 - gpr : should be <&gpr> on i.MX53 and i.MX6q.

         The phandle points to the iomuxc-gpr region containing the LVDS

         control register.

- clocks, clock-names : phandles to the LDB divider and selector clocks and to

                        the display interface selector clocks, as described in

                        Documentation/devicetree/bindings/clock/clock-bindings.txt

        The following clocks are expected on i.MX53:

                "di0_pll" - LDB LVDS channel 0 mux

                "di1_pll" - LDB LVDS channel 1 mux

                "di0" - LDB LVDS channel 0 gate

                "di1" - LDB LVDS channel 1 gate

                "di0_sel" - IPU1 DI0 mux

                "di1_sel" - IPU1 DI1 mux

        On i.MX6q the following additional clocks are needed:

                "di2_sel" - IPU2 DI0 mux

                "di3_sel" - IPU2 DI1 mux

        The needed clock numbers for each are documented in

        Documentation/devicetree/bindings/clock/imx5-clock.txt, and in

        Documentation/devicetree/bindings/clock/imx6q-clock.txt.

Optional properties:

 - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q

 - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,

               not used on i.MX6q

 - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should

   be configured - one input will be distributed on both outputs in dual

   channel mode

LVDS Channel

==

Each LVDS Channel has to contain a display-timings node that describes the

video timings for the connected LVDS display. For detailed information, also

have a look at Documentation/devicetree/bindings/video/display-timing.txt.

Required properties:

 - reg : should be <0> or <1>

 - crtcs : a list of phandles with index pointing to the IPU display interfaces

           that can be used as video source for this channel.

 - fsl,data-mapping : should be "spwg" or "jeida"

                      This describes how the color bits are laid out in the

                      serialized LVDS signal.

 - fsl,data-width : should be <18> or <24>

example:

gpr: iomuxc-gpr@53fa8000 {

        /* ... */

};

 

ldb: ldb@53fa8008 {

        #address-cells = <1>;

        #size-cells = <0>;

        compatible = "fsl,imx53-ldb";

        gpr = <&gpr>;

        clocks = <&clks 122>, <&clks 120>,

                 <&clks 115>, <&clks 116>,

                 <&clks 123>, <&clks 85>;

        clock-names = "di0_pll", "di1_pll",

                      "di0_sel", "di1_sel",

                      "di0", "di1";

 

        lvds-channel@0 {

                reg = <0>;

                crtcs = <&ipu 0>;

                fsl,data-mapping = "spwg";

                fsl,data-width = <24>;

 

                display-timings {

                        /* ... */

                };

        };

 

        lvds-channel@1 {

                reg = <1>;

                crtcs = <&ipu 1>;

                fsl,data-mapping = "spwg";

                fsl,data-width = <24>;

 

                display-timings {

                        /* ... */

                };

        };

};