Difference between revisions of "X86/TSN"

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(Undo revision 24459 by Winston.huang (talk))
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{{DISPLAYTITLE:Intel Linux for TSN validation}}
{{DISPLAYTITLE:Elkhart Lake images including TSN scripts}}
 
 
<div style="float:right;  position:fixed;  margin:0 1em 0 0;  top:200px;  right:10px;  max-height: 350px;  overflow: auto">__TOC__</div>  
 
<div style="float:right;  position:fixed;  margin:0 1em 0 0;  top:200px;  right:10px;  max-height: 350px;  overflow: auto">__TOC__</div>  
== By product ==
+
== Elkhark Lake ==
  
=== ARK ===
+
all EHL images are stored on [https://www.dropbox.com/sh/hjdm01i77di6dij/AABsYU7Rd1q4KiHSe1zPymOga/EHL this].
  
{| class="wikitable sortable" style="text-align: center" border="2"
+
{| class="wikitable" style="text-align: center" border="2"
 
|-
 
|-
! '''product'''
 
 
! '''version'''
 
! '''version'''
! '''image'''
+
! '''base image'''
 +
! '''image including TSN scripts'''
 
|-
 
|-
| <div id="1221L">ARK-1221L</div>
+
| valign="center" align="center" |  
| valign="center" align="center" | [[#MR1|MR1]]
+
{|
| align="left" | [[#20220311|EHL-intel-corei7-64-rt_20220311.wic.bz2]]
 
|}
 
 
 
=== SOM ===
 
 
 
{| class="wikitable sortable" style="text-align: center" border="2"
 
 
|-
 
|-
! '''product'''
+
| MR1
! '''version'''
 
! '''image'''
 
 
|-
 
|-
| <div id="2532">SOM-2532</div>
+
| MR2
| valign="center" align="center" | [[#MR1|MR1]]
 
| align="left" | [[#20210913|EHL-intel-corei7-64-rt_20210913.wic.bz2]]
 
----
 
 
 
[[#20211028|EHL-intel-corei7-64-rt_20211028.zip]]
 
 
 
 
|-
 
|-
| <div id="6832">SOM-6832</div>
+
| MR3
| valign="top" align="center" | [[#MR1|MR1]]
 
----
 
[[#MR3|MR3]]
 
 
 
| align="left" | [[#20211111|EHL-intel-corei7-64-rt_20211111.zip]]
 
----
 
 
 
[[#202206??|EHL-intel-corei7-64-rt_20220617.zip]]
 
 
|}
 
|}
  
== By image ==
 
 
=== MR1 ===
 
 
{| class="wikitable sortable" style="text-align: center" border="2"
 
|-
 
! '''image'''
 
! '''summary'''
 
! '''built for'''
 
|-
 
 
| valign="top" align="left" |  
 
| valign="top" align="left" |  
 
{|
 
{|
 
|-
 
|-
| EHL-intel-corei7-64-rt_20210913.wic.md5
+
| core-image-sato-sdk-intel-corei7-64.wic.md5
 
|-
 
|-
| EHL-intel-corei7-64-rt_20210913.wic.bmap
+
| core-image-sato-sdk-intel-corei7-64.wic.bmap
 
|-
 
|-
| <div id="20210913">EHL-intel-corei7-64-rt_20210913.wic.bz2</div>
+
| core-image-sato-sdk-intel-corei7-64.wic.bz2
 
|}
 
|}
  
| valign="top" align="left" |  
+
| valign="center" align="center" |  
{|
+
[[X86/TSN/EHL|click here]]
|-
+
 
| #619566-2.0
 
|-
 
| #616446-1.7
 
|-
 
| addon_EHL_616446_test-scripts_20210911_1518.tgz
 
|-
 
| kernel parameters: isolcpus=1-3 rcu_nocbs=1-3
 
 
|}
 
|}
  
| valign="top" align="left" | [[#2532|SOM-2532]]
+
<span id="EHL_Notice_for_MR3">Notice for MR3:</span>
|-
+
 
| valign="top" align="left" |
+
: BIOS setting : Chipset -> PCH-IO Configuration -> PinCntrl Driver GPIO Scheme [<span style="color:#FF0000">Enabled</span>]
{|
+
 
|-
+
== Tiger Lake ==
| EHL-intel-corei7-64-rt_20211028.zip.md5
 
|-
 
| <div id="20211028">EHL-intel-corei7-64-rt_20211028.zip</div>  
 
|}
 
  
| valign="top" align="left" |
+
all TGL images are stored on [https://www.dropbox.com/sh/hjdm01i77di6dij/AAAKWHFiUEemlKIiQJieU1lHa/TGL this].
{|
 
|-
 
| #619566-2.0
 
|-
 
| #616446-1.7
 
|-
 
| addon_EHL_616446_test-scripts_20211028_0923.tgz
 
|}
 
  
| valign="top" align="left" | [[#2532|SOM-2532]]
+
{| class="wikitable" style="text-align: center" border="2"
 
|-
 
|-
| valign="top" align="left" |
+
! '''version'''
{|
+
! '''base image'''
 +
! '''image including TSN scripts'''
 
|-
 
|-
| EHL-intel-corei7-64-rt_20211111.zip.md5
+
| valign="center" align="center" |  
|-
 
| <div id="20211111">EHL-intel-corei7-64-rt_20211111.zip</div>
 
|}
 
 
 
| valign="top" align="left" |  
 
 
{|
 
{|
 
|-
 
|-
| #619566-2.0
+
| MR4
|-
 
| #616446-1.7
 
|-
 
| addon_EHL_616446_test-scripts_20211028_0923.tgz
 
 
|}
 
|}
  
| valign="top" align="left" | [[#6832|SOM-6832]]
 
|-
 
 
| valign="top" align="left" |  
 
| valign="top" align="left" |  
 
{|
 
{|
 
|-
 
|-
| EHL-intel-corei7-64-rt_20220311.wic.md5
+
| core-image-sato-sdk-intel-corei7-64.wic.md5
 
|-
 
|-
| EHL-intel-corei7-64-rt_20220311.wic.bmap
+
| core-image-sato-sdk-intel-corei7-64.wic.bmap
 
|-
 
|-
| <div id="20220311">EHL-intel-corei7-64-rt_20220311.wic.bz2</div>
+
| core-image-sato-sdk-intel-corei7-64.wic.bz2
 
|}
 
|}
  
| valign="top" align="left" |  
+
| valign="center" align="center" |  
{|
+
[[X86/TSN/TGL|click here]]
|-
 
| #619566-2.0
 
|-
 
| #616446-1.7
 
|-
 
| addon_EHL_i225_616446_test-scripts_20220311_1506.tgz
 
|}
 
  
| valign="top" align="left" | [[#1221L|ARK-1221L]]
 
 
|}
 
|}
  
 +
== Alder Lake ==
  
=== MR3 ===
+
all ADL images are stored on [https://www.dropbox.com/sh/hjdm01i77di6dij/AACRgJ8ZZX1TQr-ZTYgcvOaIa/ADL this].
([[X86/TSN#EHL_Notice_for_MR3 |notice]])
 
  
{| class="wikitable sortable" style="text-align: center" border="2"
+
{| class="wikitable" style="text-align: center" border="2"
 
|-
 
|-
! '''image'''
+
! '''version'''
! '''summary'''
+
! '''base image'''
! '''built for'''
+
! '''image including TSN scripts'''
 
|-
 
|-
| valign="top" align="left" |  
+
| valign="center" align="center" |  
 
{|
 
{|
 
|-
 
|-
| EHL-intel-corei7-64-rt_20220617.wic.md5
+
| PV
|-
 
| <div id="202206.3F.3F">EHL-intel-corei7-64-rt_20220617.zip</div>
 
 
|}
 
|}
  
Line 162: Line 90:
 
{|
 
{|
 
|-
 
|-
| #619566-3.3 ( + #619566-3.4 Sec. 3.2.1 step 8 & 9 )
+
| core-image-sato-sdk-intel-corei7-64.wic.md5
 
|-
 
|-
| #616446-1.9
+
| core-image-sato-sdk-intel-corei7-64.wic.bmap
 
|-
 
|-
| addon_TOP_EHL_616446-1.9_20220617_1318.tgz
+
| core-image-sato-sdk-intel-corei7-64.wic.bz2
|-
 
| addon_TOP_SWREQ_14137_CAN_IBECC_USB_20220602_1212.tgz
 
 
|}
 
|}
  
| valign="top" align="left" | [[#2532|SOM-6832]]
+
| valign="center" align="center" |  
 +
[[X86/TSN/ADL|click here]]
 +
 
 
|}
 
|}

Revision as of 04:23, 20 June 2022

Elkhark Lake

all EHL images are stored on this.

version base image image including TSN scripts
MR1
MR2
MR3
core-image-sato-sdk-intel-corei7-64.wic.md5
core-image-sato-sdk-intel-corei7-64.wic.bmap
core-image-sato-sdk-intel-corei7-64.wic.bz2

click here

Notice for MR3:

BIOS setting : Chipset -> PCH-IO Configuration -> PinCntrl Driver GPIO Scheme [Enabled]

Tiger Lake

all TGL images are stored on this.

version base image image including TSN scripts
MR4
core-image-sato-sdk-intel-corei7-64.wic.md5
core-image-sato-sdk-intel-corei7-64.wic.bmap
core-image-sato-sdk-intel-corei7-64.wic.bz2

click here

Alder Lake

all ADL images are stored on this.

version base image image including TSN scripts
PV
core-image-sato-sdk-intel-corei7-64.wic.md5
core-image-sato-sdk-intel-corei7-64.wic.bmap
core-image-sato-sdk-intel-corei7-64.wic.bz2

click here