Difference between revisions of "AIM-Linux/ROM-5722"

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'''Yocto 5.0&nbsp; &nbsp; &nbsp; (Kernel 6.6.23)'''<br/> [http://ess-wiki.advantech.com.tw/view/ROM-5722_user_guide User Guide]　[https://ess-wiki.advantech.com.tw/view/Release_Note_ROM-5722_Y50 Release Note]
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'''Yocto 5.0&nbsp; &nbsp; &nbsp; (Kernel 6.6.23)'''<br/> [http://ess-wiki.advantech.com.tw/view/ROM-5722_user_guide User Guide]　[https://ess-wiki.advantech.com.tw/view/Release_Note_rom5721_Y5 Release Note]
  
 
'''Yocto&nbsp;4.2&nbsp; &nbsp; (Kernel 6.1.22)'''<br/> [http://ess-wiki.advantech.com.tw/view/ROM-5722_user_guide User Guide]　[https://ess-wiki.advantech.com.tw/view/Release_Note_ROM-5722 Release Note]
 
'''Yocto&nbsp;4.2&nbsp; &nbsp; (Kernel 6.1.22)'''<br/> [http://ess-wiki.advantech.com.tw/view/ROM-5722_user_guide User Guide]　[https://ess-wiki.advantech.com.tw/view/Release_Note_ROM-5722 Release Note]

Revision as of 02:17, 11 August 2025


RTENOTITLE

Advantech ROM-5722 SMARC 2.0/2.1 is powered by NXP i.MX8M Plus SOC which includes up to 4 Arm Cortex-A53 cores in combination with one Cortex-M7 real time processor and Vivante GC7000UL graphics engine. It provides USB2.0, Gigabit Ethernet, MIPI-CSI, PCI Express, Dual channel LVDS

  • NXP Arm® Cortex®-A53 i.MX8M Plus Quad/Dual up to 1.8 GHz
  • 1 x Arm Cortex-M7 core
  • Onboard LPDDR4 6 GB, 4000MT/s memory
  • 1 x 4 lane MIPI-CSI,1 x Dual channel LVDS or 1 x Display Port
  • 4 x USB2.0, 1 x USB 2.0 OTG, 4 x UART, 5 x I2C, 14 x GPIO, 1 x PCIe3.0, 2 x Gigabit LAN, 2 x CAN-FD
  • Neural network accelerator up to 2.3 TOPS
  • Supports Ycoto Linux

Find Other Products

Yocto

Yocto 5.0      (Kernel 6.6.23)
User Guide　Release Note

Yocto 4.2    (Kernel 6.1.22)
User Guide　Release Note

Yocto 4.0    (Kernel 5.15.52)
User Guide　Release Note

Yocto 3.0    (Kernel 5.4.70)
User Guide　Release Note

Windows10

Windows 10 IoT Enterprise  
User Guide　Release Note

 

App Add on
Launcher
Protocal
Diagnostic
DevelopSDK
Security
Edge AI
Management
WISE-DeviceOn
Documentation
Datasheet
Manual
3D Model
Certification
Design Guideline
Layout Checklist
Schematic Pinout

 

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